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AUSTIN, Texas, May 2, 2018 - The DDR PHY Interface (DFI) Group right now released model 5.0 of the specification for interfaces between excessive-speed memory controllers and bodily (PHY) interfaces to support the necessities of future cell and server memory standards. The DFI specifications, widely adopted throughout the memory trade, enable greater interoperability. The DFI Group included a number of interface enhancements in this newest specification. The brand new version of the specification provides protocol help for the most recent DDR and low-energy memory applied sciences. Previous versions of the specification defined memory training across the interface between the memory controller and the PHY. The new specification completely transitions to PHY-independent coaching mode the place the PHY trains the Memory Wave Method interface without involving the controller. Different interface enhancements include lower power enhancements, offering a PHY-unbiased boot sequence, expanding frequency change help, and defining new controller-to-PHY interface interactions. "The industry is starting to embrace new low-power and DDR memory technologies, together with high-performance devices akin to servers, storage, and networking; autonomous vehicles; and low-power handheld devices and IoT," acknowledged John MacLaren, DFI Group chairman and Cadence design engineering architect.



"The DFI Group, consisting of experts from main firms in the business, is enthusiastic to contribute to enabling this transition with the most recent release of the DFI specification. "Adopting open and customary interfaces like the new DFI 5.0 specification for high-pace memory controller and PHY interface allows AMD to efficiently and successfully undertake new memory requirements as we ship excessive-efficiency products to our customers. "Cadence has been a key contributor to the DFI 5.Zero commonplace, which helps to make sure interoperability between DDR PHYs and DDR controllers, significantly for future memory units," stated Marc Greenberg, group director, product marketing, DDR, HBM, flash/storage and MIPI IP. "As a number one supplier of DDR IP and Verification IP, Synopsys makes significant investments to make sure that our DesignWare® controller and PHY IP are compliant to industry requirements reminiscent of DFI," said Navraj Nandra, Sr. Director of selling for Interface and Analog IP options at Synopsys.



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